In fabrication of VLSI and ULSI integrated circuits, the use of fully recessed isolation, such as a process known as the "shallow trench" technique, has been used in submicron manufacturing processes to reduce surface topography related process problems associated with non-planar surfaces.
A typical structure would be formed in the following manner:
1. patterning and etching trenches in the field areas; PA0 2. passivating and filling the trenches with a dielectric material, typically an oxide, e.g. silicon dioxide; and PA0 3. planarizing the wafer surface.
There are numerous known methods of planarizing wafers during fabrication of integrated circuits, for example, block resist and resist etch back, block resist and spin on glass. A promising and simple method of choice is chemical mechanical polishing (CMP). CMP provides full wafer planarization without additional masking or coating steps. However, one of the difficulties encountered with CMP for trench planarization is the "dishing" effect which occurs in wide trenches (i.e..about.30 .mu.m), typical of a fully recessed field structure. "Dishing" is particularly severe in trenches wider than 100 .mu.m and the "dishing" effect during polishing results in thinning of the dielectric in wide trenches only, and much effort has been directed to modify the polish process, equipment and materials attempt to reduce and control the dishing effect.